1. Field of the Invention
The present invention relates to a method of fabricating the capacitors and devices of a semiconductor device. More particularly, the present invention relates to a method of fabricating the dual polysilicon layer capacitors and the devices of a dual operation voltage mixed-signal integrated circuit.
2. Description of the Related Art
On the eve of the twenty-first century, semiconductor applications continue to expand. A large quantity of semiconductor devices having a variety of functions is used in computer systems, communication equipment and many consumer electronic products.
To cater to some specific customer applications, application-specific integrated circuits (ASIC) are fabricated. In addition, in order for an electronic product to be light, compact and speedy, system on chip (SOC) design is often adopted in the fabrication of semiconductor devices. In other words, separately manufactured electronic devices are now formed in a single silicon chip. Currently, a type of application-specific circuit known as a mixed-signal integrated circuit has been developed. The mixed-signal circuit is formed by integrating a capacitor and a complementary metal oxide semiconductor (CMOS) device together. At first, all the CMOS devices operate at a single gate voltage. Recent advances in manufacturing technologies have made it possible to include two or more types of CMOS devices, each operating at its own operational voltage. For example, an integrated circuit having CMOS devices capable of working in dual or even triple voltage mode are fabricated on a silicon chip.
FIGS. 1A through 1C are schematic cross-sectional views showing the steps for producing the gate oxide layers of a conventional integrated circuit that operates in dual voltage mode.
As shown in FIG. 1A, gate oxide layers 102 are formed on portions of a substrate 100. The substrate 100 has a well region 104 and shallow trench isolation structures 106 therein. The gate oxide layer 102 is formed by thermal oxidation. A patterned photoresist layer 108 is formed over the substrate 100, which comprises substrate regions 100a and 100b. The photoresist layer 108 covers the substrate region 100a for forming the desired high operation voltage devices so that the substrate region 100b for forming the desired low operation voltage devices is exposed.
As shown in FIG. 1B, the gate oxide layer 102 on substrate regions 100b is removed while retaining the gate oxide layer 102a on the substrate region 100a.
As shown in FIG. 1C, the patterned photoresist layer 108 is removed and then another thermal oxidation is carried out. Hence, a gate oxide layer 110 is formed on the substrate 100 in the substrate region 100b. Meanwhile, moisture and oxygen can still diffuse and react with the existing gate oxide layer 102a to form a thicker oxide layer 112.
Consequently, by controlling the parameters during these two thermal oxidations, gate oxide layers of different thicknesses are formed in various regions. Thus, devices having the desired working voltages are formed in desired locations.
In the conventional method of fabricating the dual thickness gate oxide layer, a portion of the gate oxide layer has to be covered by a photoresist layer. Hence, if the photoresist layer is not thoroughly removed, residual defects may remain above the gate oxide layer to compromise device reliability. In addition, if a capacitor having polysilicon upper and lower electrodes needs to be formed at the same time as the gate terminal, only the polysilicon gate layer can serve as the lower electrode of the capacitor. In other words, to form the capacitor, steps still have to be undertaken to form a dielectric layer above the lower electrode followed by an upper electrode above the dielectric layer. Hence, production time and cost are increased.